Semiconductor
When resistance becomes the bottleneck, AI infrastructure may shift from hotter chips to cryogenic, lossless computing
The Cold Computers: Superconducting AI Infrastructure at Four Kelvin
When the physics of resistance itself becomes the problem, the industry stops fighting it and removes it entirely
There is a number that keeps appearing in conversations about the future of AI infrastructure, and it is not a model benchmark or a parameter count. It is a temperature.
Four Kelvin. That is −269 degrees Celsius. Two degrees above the coldest temperature physically possible in the universe. And it may be the temperature at which the economics of AI, an industry now committing hundreds of billions of dollars to data centers whose single largest constraint is the electrical grid, stop being hostage to the heat losses of ordinary matter.
That is where the next generation of computing may happen, not in a warmer, faster, denser version of today’s data centers, but in a refrigerated cylinder the size of a rack, running logic that has no resistance, loses almost no energy to heat, and switches a thousand times faster than anything built on silicon today.
To understand why that number matters, it helps to remember where this series started.
The first article in this series was about what happens when Moore’s Law, shrink the transistor, performance follows, stops being a free ride. The industry’s answer was to reinvent everything around the transistor simultaneously: the physics of lithography, the geometry of packaging, the architecture of power delivery. Smaller wasn’t enough anymore. The industry went deeper.
The second article was about what happens when the transistor itself is no longer the bottleneck, when the problem is moving data between transistors, between chips, between racks. The answer there was light. Silicon photonics replaced copper with photons, cutting energy per bit by roughly 80% and turning the data center from a room full of electrons into something closer to a room full of light.
This article is about the next constraint. Not the transistor. Not the wire. The physics of resistance itself.
Every electron moving through a conductor loses energy to the material it moves through. We call it resistance, and we have been engineering around it for a century, thinner wires, better materials, lower voltages, higher frequencies. But in a data center running hundreds of megawatts to power AI training clusters, engineering around resistance is no longer enough. The losses have become structural. The heat has become the problem.
The question the industry is now asking is not how to reduce resistance. It is whether resistance can be removed from the equation entirely.
The material that changes the physics
Certain materials, when cooled below a critical temperature, enter a state where electrical resistance disappears completely. Not diminishes. Disappears. Electrons move through the material without losing energy to it. This is superconductivity, and it has been known since 1911.
What has not been known, until recently, is how to build a computer out of it.
The transistor, the basic unit of every processor built in the last sixty years, does not work in a superconducting system. It is replaced by something called a Josephson junction. The physics of how it works is less important than what it does: instead of switching between high and low voltages the way a transistor does, a Josephson junction emits a single, tiny, precisely quantized pulse of magnetic energy when it switches. That pulse, vanishingly small, lasting roughly one picosecond, becomes the basic unit of information
A Josephson junction is a quantum mechanical device made of two superconducting layers separated by a thin insulating barrier that acts as the primary switching element in superconducting computing. Instead of switching between high and low voltages like a traditional CMOS transistor, a Josephson junction emits a single, tiny, precisely quantized pulse of magnetic energy when it switches.
The difference in energy between a transistor switching and a Josephson junction switching is not incremental. A modern transistor switches at around 500 millivolts. A Josephson junction switches at around one millivolt. The energy difference is not a factor of two or ten. It is potentially tens of thousands of times less energy per operation.
And because the wires carrying those pulses are superconducting, almost none of that energy is lost in transit. The signal arrives where it is going intact, at speeds conventional processors cannot reach. Modern CPUs run at 3 to 5 gigahertz. Superconducting circuits have already demonstrated operation beyond 20 gigahertz, with some circuits exceeding 100 gigahertz.
This is not a faster transistor. It is a different physics of computing.
The manufacturing problem that just became solvable
For decades, superconducting computing stayed in research labs for a simple reason: nobody could figure out how to build it at scale. The materials were difficult. The fabrication processes were incompatible with existing semiconductor manufacturing. The economics made no sense without a production pathway, and there was no production pathway without economics to justify it.
IMEC, the Belgian research institute where much of the semiconductor industry’s next decade gets invented before it reaches commercial fabs, decided to look at this problem again. Not because the physics changed, but because the manufacturing constraints did.
At the 2024 IEEE International Electron Devices Meeting, IMEC demonstrated the three critical building blocks of a superconducting digital circuit: NbTiN-based interconnects, Josephson junctions with amorphous silicon barriers, and MIM capacitors, devices that outperform state-of-the-art superconducting technology and meet the target specifications for superconducting digital systems.
The material at the center of this is niobium titanium nitride, NbTiN. Unlike conventional niobium, NbTiN can withstand the temperatures used in standard CMOS recipes and reacts much less with its surrounding layers. That compatibility is the breakthrough. It means superconducting circuits can be fabricated on standard 300mm wafers using processes the industry already knows how to run. (IMEC)
The insulating layer inside the Josephson junction, the thin barrier sandwiched between two superconducting layers, was replaced with amorphous silicon. That change made the junction easier to manufacture at the densities a real computing system requires.
IMEC’s superconducting compute strategy aims at delivering up to 100x higher energy efficiency and 10–100x better performance than current CMOS processors. (arXiv)
The system IMEC modeled from these building blocks, 100 superconducting circuit boards, would fit in a shoebox and deliver over 20 exaflops of compute at around 500 kilowatts of power. For reference, the most powerful supercomputer in 2024 peaked at 1.7 exaflops and consumed hundreds of megawatts. Those are modeled projections, not demonstrated results. But they are projections grounded in building blocks that have now been physically demonstrated at IEDM.
And the platform is moving, not standing still. At IEDM 2025, IMEC reported the next round of progress: a new Josephson junction process module enabling higher junction densities, and functional flux-trapping structures that improve circuit reliability, the unglamorous engineering that separates a demo from a technology.
One caveat that belongs in the same sentence as the shoebox: the shoebox-sized computer requires a rack-sized insulated cylinder, which in turn requires a cryogenic refrigerator the size of three more racks. The cryogenic cooling system is real infrastructure, not a footnote. The question is whether its energy cost is justified at scale, and IMEC’s analysis suggests that for systems at the size of today’s AI data centers, the math inverts. The cooling penalty becomes smaller than the efficiency gain. For a laptop, this makes no sense. For a gigawatt AI cluster, the economics look very different.
Two more caveats, because this technology has broken hearts before. The first is memory: Josephson junctions make superb logic and poor storage, and dense superconducting memory remains an unsolved problem, the same obstacle that helped stall every previous attempt to commercialize the technology, from IBM’s program in the 1980s onward. IMEC’s system design works around it rather than through it, and it is the honest weak point. The second is time: no commercial superconducting computer exists, and even the optimistic path runs through years of process maturation, think early-to-mid 2030s for systems, not products next quarter. What changed is not the distance to the destination. It is that, for the first time, there is a road.
The constraint that became a different architecture
While IMEC was solving the manufacturing problem from inside the global semiconductor ecosystem, something else was happening at the edge of it.
Huawei, cut off since 2019 from global chip manufacturers by US sanctions and unable to access ASML’s EUV lithography machines, announced at the IEEE International Symposium on Circuits and Systems in Shanghai on May 25, 2026 a new chip design framework called LogicFolding. The announcement carried its own theater: it was delivered by He Tingbo, president of Huawei’s chip unit HiSilicon, returning to public view after seven years of silence.
LogicFolding folds traditional 2D circuits into 3D vertical structures, distributing logic gates on critical paths across stacked wafer layers connected by ultra-fine-pitch hybrid bonding, reducing the resistive and capacitive load of signal propagation and boosting transistor density without requiring lithography improvements that China cannot currently access. (SCMP)
Paired with it, Huawei introduced the Tau Scaling Law, a new guiding principle that replaces the traditional goal of shrinking transistors with a focus on cutting the time it takes signals and data to move through chips and computing systems. Note what that is: resistance times capacitance. Tau is the RC time constant. Huawei’s answer to the same physics IMEC is attacking is not to remove resistance but to shorten the distance it acts over.
The Tau ($\tau$) Scaling Law: is an architectural framework introduced by Huawei that shifts the focus of chip design from shrinking physical transistors to minimizing signal delay, reducing the resistance-capacitance time constant ($\tau = RC$) across 3D stacked circuits to boost speed and efficiency without relying on advanced lithography.
The first commercial test arrives this autumn, when LogicFolding debuts in Kirin smartphone chips. Huawei claims the dual-layer architecture lifted transistor density in the Kirin 2026 from 155 to 238 million transistors per square millimeter, a 55% jump, roughly three years of traditional node scaling, alongside a 41% power-efficiency gain. (Tom’s Hardware) Huawei targets 1.4nm-class transistor density by 2031. TSMC, for context, is already running volume production at 2nm and has a 1.4nm process slated for mass production in 2028.
And Huawei is not treating this as a one-off. On July 3, 2026 the company published an expanded V2 of the Tau paper, projecting LogicFolding’s evolution from dual-layer critical-path optimization to full multi-layer architectures, three or more active layers per package, and, notably, extending the roadmap beyond smartphones to its Ascend AI accelerators, with the Ascend 990 expected around 2030. (TrendForce) The mobile chip is the validation platform. The AI datacenter is the destination.
The claims are ambitious and the skepticism is warranted. Huawei’s assertion of having designed and mass-produced 381 chips based on the Tau Scaling Law over six years remains self-declared and without external academic validation. The engineering objections are specific: Shanghai research firm ICwise estimates that folding circuits into multiple active layers raises heat density five to ten times, and traditional 2D EDA design tools cannot yet handle 3D LogicFolding layouts, a gap China’s domestic EDA industry is still racing to close. (TNW) Independent analysts note that a stacked design can produce effective density gains without resolving the full process, yield, power, thermal, and device-performance problems associated with true 1.4nm-class manufacturing. Even the most prominent outside endorsement was double-edged: Nvidia’s Jensen Huang called the Tau approach a breakthrough while adding that he sees no challenge to TSMC in it.
But the significance of LogicFolding is not whether it delivers on every claimed metric. The specificity of LogicFolding lies less in the architectural idea than in the context in which it is mobilized: that of a company cut off from leading Western foundries and deprived of access to EUV lithography machines.
Huawei didn’t invent a new physics because it wanted to. It invented a new scaling law because the old one was made unavailable to it. Constraint, again, as the engine of reinvention.
The accidental infrastructure
There is one more thread worth pulling.
Superconducting computing doesn’t have a manufacturing ecosystem yet. Building one from scratch would require the kind of investment that only makes sense if there are products to justify it, a chicken-and-egg problem that kept the technology in labs for decades.
But the semiconductor industry is currently pouring billions into something that shares almost every engineering challenge with superconducting classical logic: quantum computing. Both rely on superconducting materials. Both operate at cryogenic temperatures. Both require advanced packaging and fabrication processes that work near absolute zero.
In May 2026, that overlap acquired a name and a dollar figure. IBM and the US Department of Commerce announced Anderon, America’s first purpose-built quantum foundry, a standalone company headquartered in Albany, New York, backed by up to $1 billion in CHIPS incentives and a matching $1 billion from IBM, operating a 300-millimeter quantum wafer fab that will initially focus on superconducting qubit wafers and related electronics. (Bloomberg) Read that specification again: a government-subsidized, 300mm, superconducting-wafer foundry. It is being built for qubits. But nearly everything it de-risks, the materials, the cryo-compatible processes, the supply chain, the trained workforce, is exactly what superconducting classical computing has been missing.
The industry is building the factory for one technology and inadvertently enabling another. That is not a coincidence or a plan. It is what happens when multiple bets on post-silicon computing converge on the same underlying physics.
What the series has been about
Three articles. Three constraints. Three reinventions.
Moore’s Law ended the era of free scaling and forced the industry to reinvent lithography, packaging, and power delivery simultaneously, using AI, among other tools, to navigate a design space too complex for human engineers alone.
Copper’s limits ended the era of purely electronic data movement and pushed light into the package, silicon photonics turning AI data centers into optical fabrics, with waveguides printed by the same fabs that print transistors.
And now resistance itself, the fundamental physics cost of moving information through matter, is the constraint. The industry’s answer is to remove it: superconducting materials that carry information without loss, at temperatures so cold they fall outside ordinary intuition, in pulses so small and fast the numbers require a moment to absorb.
Huawei’s LogicFolding sits alongside this not as a superconducting technology but as the same underlying logic applied under different pressure. When the standard path is closed, you find a different physics. When shrinking transistors is unavailable, you fold them. When resistance is the problem, you remove it, or you shorten the wire it lives in.
The AI infrastructure story is not, in the end, a story about models or data or compute budgets. It is a story about what happens when demand for intelligence runs ahead of what the available physics can support, and an industry, under pressure from multiple directions at once, starts rewriting the physics.
The intelligence and the infrastructure are still designing each other. They are now doing it in the cold.
Sources:
https://www.economist.com/china/2026/07/05/has-china-obtained-the-worlds-most-important-machine?utm_campaign=shared_article
https://www.economist.com/business/2026/07/07/chinas-semiconductor-industry-is-racing-to-catch-the-wests?utm_campaign=shared_article
https://www.economist.com/technology-quarterly/2024/09/16/ai-has-returned-chipmaking-to-the-heart-of-computer-technology?utm_campaign=shared_article
https://www.economist.com/science-and-technology/2026/07/08/the-future-of-chipmaking-looks-more-like-manhattan-than-silicon-valley?utm_campaign=shared_article